module multiplicador#(parameter N = 16)(G,reset,clk,bus_in,out);
    input G, reset, clk;
    input [N-1:0] bus_in;
    output [2*N-1:0] out;

    wire [2:0] Csignal;
    wire Z, q;
    wire [3:0] n_contador;
    wire [N-1:0] q_Q;
    wire shift_Q, Q_sout;
    wire shift;
    wire [N-1:0] q_B ;
    wire [N-1:0] pa_out;
    wire carry;
    wire load_Q;
    wire load_B;
    wire load_A, A_sout;
    wire reset_A;
    wire [N-1:0] q_A;
    wire load_C, C_sout;
    wire reset_C;
    wire q_C;
    wire enable_counter;
    wire load_counter;
    controlUnit # ((N)) cu(Q_sout, Z, G, reset, clk, Csignal);
    zero_detect # (4) zd(n_contador,Z);
    shiftreg # ((N)) Q(shift, load_Q, bus_in, A_sout, clk, Q_sout, q_Q, reset);
    register # ((N)) B(bus_in, load_B, q_B, clk, reset);
    ParallelAdder # ((N)) pa(q_A, q_B,0, pa_out, carry);
    shiftreg # ((N)) A(shift, load_A, pa_out, C_sout, clk, A_sout, q_A, reset_A);
    shiftregC C(shift, load_C, carry, 0, clk, C_sout, q_C, reset_C);
    counter #(4) coun(load_counter, enable_counter, clk, n_contador);

    assign q=q_A[0];
    assign shift = Csignal[2];
    assign enable_counter = Csignal[2];
    assign load_A = Csignal[2] &  Csignal[0];
    assign load_C = Csignal[2] &  Csignal[0];
    assign load_B = Csignal[1] & Csignal[0];
    assign load_counter = Csignal[1] & Csignal[0];
    assign reset_A = Csignal[1] & ~Csignal[0];
    assign reset_C =Csignal[1] & ~Csignal[0];
    assign load_Q = Csignal[1] & ~Csignal[0];
    assign out = {q_A,q_Q};
endmodule
